1. Field of Use
This invention relates to cache systems and more particularly to cache systems which include command buffer apparatus.
2. Prior Art
It is well known that many data processing systems employ a memory hierarchy which includes a main store and a cache unit. Generally recognized are the cost advantages of having such a cache unit contain a limited number of blocks to minimize the size of the memories included therein. However, others have recognized certain disadvantages resulting from such storage limitations.
In overcoming such disadvantages, some high speed memory systems provide a high degree of overlaps or concurrency of commands. However, in providing such overlap, it has been found that this introduces additional complexity in terms of the transfer of information between the cache unit and main store as well as in the sequencing of commands. One system improves the transfer of data between main store and the cache unit through the inclusion of a memory command buffer which includes apparatus to permit sequential execution of a portion of a stored instruction involving the system interface unit between the main store and the cache unit and apparatus for providing sequential execution of a portion of the stored instruction involving the cache unit. For further information regarding this system, reference may be made to the copending patent application entitled "A Cache Memory Command Circuit", invented by Charles P. Ryan, bearing Ser. No. 861,228, filed on Dec. 16, 1977 and assigned to the same assignee as named herein.
While the above command buffer arrangement improves the transfer of data between main store and the cache unit, the number of different types of commands which could be processed at any one time was somewhat limited. This was found to cause delays in the transferring of commands to main store.
Accordingly, it is a primary object of the present invention to provide an improved arrangement for controlling the transfer of commands and data between a cache unit and main store.
It is a further object of the present invention to provide a cache unit which permits a high degree of efficiency in transferring commands and data with minimal amount of cost and complexity.
It is still a further object of the present invention to provide an arrangement for transferring commands and data between a cache unit and main store with a high degree of reliability.